Implementation and Hardware-Level Validation of a 36 V BLDC Motor Drive Using Artix-7 FPGA
DOI:
https://doi.org/10.62146/ijecbe.v4i1.244Keywords:
BLDC motor drive, FPGA, Hall sensor, PWM control, six-step commutation, dead-time insertionAbstract
This paper presents an Artix-7 FPGA-based implementation and validation of a 36 V BLDC motor drive for open-loop no-load operation. The proposed controller combines Hall-sensor sixstep commutation, counter-based PWM generation, bidirectional phase sequencing, and deadtime-protected gate output logic in programmable hardware. The study emphasizes hardwarelevel validation, including the consistency of Hall-sector decoding, PWM scaling, and inverter output behavior, rather than closed-loop speed regulation. The design was verified using Verilog simulation and experimentally tested with a three-phase inverter, a 20 kHz PWM carrier, and a 10 - bit duty cycle. The measurements confirmed the expected PWM-driven phase, low-side return path, and floating phase behavior for adjacent Hall states. No-load characterization was then performed in both clockwise and counterclockwise directions. The measured speed increased almost linearly with duty cycle and reached approximately 2425 r/min at full duty cycle, while the supply current increased to about 0.49 A. The minimum start duty was 2% in both directions, and the minimum sustain duty was 1.8% and 1.7% for clockwise and counterclockwise rotation, respectively.
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